For decades, power delivery in data centers has largely been treated as a secondary problem. As long as processors could be fed the right voltages, and as long as the rails remained stable under normal operation, the exact structure of the power tree was not something that needed constant reinvention. Compute dictated performance, while power delivery followed behind and adapted itself to whatever the hardware needed.

However, that model is starting to break down, and the reason for this is simple: AI workloads are changing the way compute behaves at a system level.

Traditional server processors could certainly draw a lot of power, but their behavior was generally predictable enough that existing rack architectures, intermediate buses, and point-of-load conversion stages could keep things under control. AI accelerators are a different story. Their power demand is not just high, it shifts around depending on the workload, and this means that the power delivery system is no longer dealing with something steady and well behaved. Instead, it has to cope with sudden changes in demand, much tighter thermal limits, and hardware densities that older architectures were never really designed for.

One of the clearest signs that this is happening can be seen by looking at several recent announcements from companies that, at first glance, appear to be doing very different things. NXP is focusing on real-time data transport and distributed control in robotic systems, STMicroelectronics is pushing 800 VDC power distribution deeper into the rack toward the GPU, Texas Instruments is exploring two-stage conversion paths that move directly from 800 V to near-core voltages, and Navitas is demonstrating direct 800 V to 6 V conversion that removes the intermediate bus stage entirely. On paper, these are separate developments. In reality, they are all responding to the same system pressure, and they are all doing so in ways that tie back to NVIDIA’s evolving reference architecture.

The Workload Is Starting to Define the Power Tree

Historically, data center power design worked because the workload itself did not force constant architectural change. Engineers could build a reasonably flexible power tree, distribute losses across several stages, and rely on intermediate rails such as 48 V or 54 V to strike a balance between current handling, efficiency, and layout practicality. This was not perfect but it worked well enough, however, AI infrastructure is starting to force a rethink.

As racks become denser and accelerators pull more power in less space, those older intermediate stages begin to look less like sensible engineering compromises and more like limitations that the rest of the system has to work around. Every extra conversion stage adds loss, heat, hardware, and complexity, and while that may have been acceptable in more conventional servers, it becomes far harder to justify when the rack is already struggling with power density, cooling, and transient response.

This is why 800 VDC distribution is suddenly getting so much attention. Higher distribution voltage means lower current at the rack level, which immediately reduces some of the stress on the infrastructure. But this also creates a new question, and it is arguably the most important one in all of this: where exactly should the voltage be stepped down, and how many stages should that process involve?

Different companies are answering that question in different ways. Some are moving conversion closer to the load, some are reducing the number of stages, and some are trying to remove intermediate layers entirely. These are not random variations, they are different responses to the same fundamental problem.

Removing Stages Does Not Remove Difficulty

At first glance, removing conversion stages sounds like an easy win. Fewer stages should mean higher efficiency, lower cost, and less wasted board area. And to be fair, that is true to a point. The problem is that removing stages does not remove the electrical stress inside the system, it just moves it.

When multiple stages are used, the burden is spread out. Losses are distributed, thermal loading is easier to manage, and different parts of the system can absorb different problems. Once those stages disappear, all of that stress begins to concentrate into a much smaller electrical and physical space. Current density rises closer to the load, thermal behavior becomes more localized, and transient response becomes much harder to manage because there is less distance and less structure in the system to smooth things out.

This is one of those issues that can be missed very easily if you only look at block diagrams. On paper, fewer stages look cleaner. In reality, layout becomes more sensitive, parasitics become more influential, and design decisions that used to be fairly independent start interfering with each other. A routing decision can suddenly affect thermal behavior, and a thermal choice can influence switching performance. To make matters worse, once high-density AI hardware is involved, there is often very little spare area available to solve those problems gracefully.

Why NVIDIA Keeps Appearing in the Story

What is particularly striking about all of this is not just that multiple power companies are talking about 800 VDC, lower intermediate rails, or fewer conversion stages. It is that they are all, in one way or another, talking about NVIDIA at the same time.

This matters because it suggests that NVIDIA is no longer just setting the pace for compute performance. It is also helping define the system constraints around which other companies are now designing. In other words, power architecture is no longer being built around a vague idea of future server needs. It is increasingly being built around the practical realities of feeding NVIDIA-class AI hardware and that is a very different situation from the one the industry was used to in the past.

Normally, semiconductor vendors would develop their own devices, reference designs, and supporting power architectures with a relatively broad market in mind. Now, however, the gravitational pull of AI infrastructure is strong enough that companies are aligning their hardware around a common reference direction. Some are focusing on conversion stages, some on data movement, and some on control, but the center of gravity is clearly the same.

Power Design Is Becoming Workload-Specific

For a long time, it made sense to think of data center power delivery as something fairly generic. Different servers would have different loads, of course, but the overall architecture did not need to change dramatically from one application to another. A rack was a rack, a bus was a bus, and the power system only needed to be flexible enough to cover a broad range of use cases. That approach is becoming harder to defend.

AI workloads are not just larger versions of older workloads. They create different electrical conditions, different thermal conditions, and different constraints on how power needs to be moved around the system. This means that power delivery is starting to become workload-specific in a way that was not previously necessary. Engineers are no longer just asking how to deliver power efficiently. They are asking how to deliver power efficiently to a very particular class of hardware, under a very particular set of conditions, with as little wasted space and overhead as possible.

Of course, the industry has not settled on a single answer yet, and it probably will not any time soon. Some architectures will keep more stages for the sake of flexibility, while others will push toward maximum density and minimal conversion overhead. However, the broader direction is becoming difficult to ignore. The old separation between compute and power is fading, and power delivery is no longer just supporting the workload. It is starting to be shaped by it.